1. Field of the Invention
The present invention relates to a high-level synthesis method and apparatus for automatically generating a logic circuit for a semiconductor integrated circuit (LSI) represented by a behavioral description in which processing behaviors are described, and also relates to a method for producing a logic circuit using the high-level synthesis method for logic circuit design, and a recording medium. More particularly, the present invention relates to a high-level synthesis method and apparatus for automatically generating an interface circuit used to interface with a bus having a predetermined protocol so as to perform data transfer with an external circuit, such as a general-purpose CPU, based on a behavioral description described in a language having a high level of abstractness, such as the C language, with the method and apparatus being used to synthesize a hard-wired circuit, and also relates to a method for producing a logic circuit using the high-level synthesis method for logic circuit design, and a recording medium.
2. Description of the Related Art
Recent micro processing technologies have allowed larger system LSIs. A development environment in which such system LSIs can be efficiently designed and tested is much sought after.
In the 1990s, a logic synthesis tool has been developed into practical use. Following this, a behavioral synthesis tool for synthesizing a description having a register transfer level (hereinafter referred to as an RT level) based on a behavioral description in which behaviors are described excluding information on hardware structure has been at a practical stage. The behavioral synthesis tool can generate LSI designs, comparable to those manually produced, in a shorter period of time.
When such a behavioral synthesis tool is used, a designer can concentrate his or her effort on designing an algorithm, which determines an essential behavior of an LSI, that largely relies on manual work.
At an early stage of the designing of a large digital LSI, such as a system LSI, an algorithm of an entire system is first studied and tested (this process is referred to as an xe2x80x9calgorithm designxe2x80x9d). Here, a software description language, such as a programming language (e.g., the xe2x80x9cC languagexe2x80x9d), is used to design and test an algorithm on a workstation or a personal computer. Subsequently, individual processes required in a system are described with a hardware description language into behavioral descriptions which will be tested. That is, an algorithm previously described with a software description language is described again with a hardware description language into a behavioral description. Hence, conventionally, a method (high-level synthesis method) for synthesizing a circuit based on an algorithm of an entire system or behavioral descriptions using the C language has been proposed. Such a conventional technique is, for example, disclosed in Japanese Laid-Open Publication No. 10-116302, entitled xe2x80x9cMethod for Designing Integrated Circuit and Integrated Circuit Designed by the Methodxe2x80x9d.
At present, a language having a high level of abstractness, such as the xe2x80x9cC languagexe2x80x9d, is used to describe a behavior of hardware which realizes an application, such as audio or video processing, and to synthesize a hardware circuit (high-level synthesis).
In the case of the development of a large system, a part of the processing may be implemented by software which is executed by a processor, thereby facilitating the modification of specifications or the extension of functions. In this case, a system is constructed by combining a plurality of functional blocks, such as an ASIC (Application Specific Integrated Circuit), a CPU (Central Processing Unit) for executing software, and a memory. In such a system, data transfer between each functional block is performed on a bus having a predetermined transfer protocol. Therefore, a bus interface circuit needs to be attached to each functional block in order to interface between the functional block and a bus.
The bus interface circuit is operated in accordance with the protocol. The bus interface circuit interprets a control signal or an address, and transfers data on a bus to a resource (memory element) in each functional block or drives desired data from each functional block and places the data on a bus. Since these behaviors are primitive compared to an application executed by each functional block, it is not efficient to describe the behaviors into behavioral descriptions and synthesize circuits corresponding to the behaviors. Further, behavioral synthesis is not recommended for interface circuits which have fixed timing. This is because the timing of the data transfer is fixed due to scheduling of behavioral synthesis in which a logic circuit is generated based on a behavioral description which lacks information on circuit structure.
Further, if a constraint relating to the timing of data transfer is added, an interface circuit can be synthesized which is compatible with its timing specification. In this case, however, a behavioral description for generating the interface circuit may be complicated, other synthesized circuit portions may have poor performance, the synthesized interface circuit may occupy a large area in an actual LSI, or the like, which are disadvantages.
To avoid this, conventionally, an interface circuit is separately designed, mainly, by manual work and attached to an application section. FIG. 24 is a design flowchart showing such a conventional technique. As shown in FIG. 24, in a conventional design technique, circuit portions other than an interface circuit are synthesized in accordance with a process flow from an xe2x80x9cbehavioral descriptionxe2x80x9d via predetermined processes to xe2x80x9cRT level circuit descriptionxe2x80x9d. However, only the interface circuit is separately designed by manual work. The xe2x80x9cRT level circuit descriptionxe2x80x9d and the design of the interface circuit are combined into an xe2x80x9centire circuit descriptionxe2x80x9d.
As shown in FIG. 24, the aforementioned predetermined processes include: an xe2x80x9cbehavioral description analyzing sectionxe2x80x9d for parsing a behavioral description in which processing behaviors are described; a xe2x80x9ccontrol data flow graph (hereinafter referred to as CDFG) generation sectionxe2x80x9d for representing a dependence relationship between operations in the behavioral description in terms of execution order; a xe2x80x9cscheduling sectionxe2x80x9d for successively allocating time to each operation, input, and output step in CDFG; an xe2x80x9callocation sectionxe2x80x9d for allocating an operator, a register and input and output pins required to execute a scheduled CDFG to nodes; a xe2x80x9cdata path generating sectionxe2x80x9d for generating a circuit path (e.g., a multiplexer) corresponding to a data-dependent branch in a CDFG; a xe2x80x9ccontroller generating sectionxe2x80x9d for generating a controller which controls an operator, a register, and a multiplexer generated by allocation and data path generation. These predetermined processes are described in detail later.
In the above-described conventional technique, the interface circuit is designed by manual work. In this case, if an application is complicated and data transfer via a bus is required between a number of resources (memory elements), such as communication paths, memories, and registers, the design of interface circuits is significantly complicated for manual work and errors are likely to occur.
Further, since interface circuits are designed separately from an application, every time the application is changed and the number of resources or the type of data is changed, interface circuits need to be modified by manual work.
In most design developments of circuits, the specifications of the circuits are often changed. If inputs and outputs of a circuit are changed, the interface circuits have to be modified. Modification of circuits is a time-consuming task, resulting in extension of an increased design time.
Errors are likely to occur in manual design. Further, data transfer to and from a memory via a bus is typically performed. In conventional manual design, memory addresses for data transfer need to be managed, which is significantly complicated for manual work and errors are likely to occur.
As described above, if a system is large, a part of processing is sometimes implemented by software executed by a CPU. In this case, a large system requires a CPU for executing software, and consists of hardware and software. Hardware needs to be developed apart from software. In order to perform data transfer between hardware and software, addresses etc. of resources in a CPU need to be designated. Address information needs to be managed, in which errors are likely to occur if managed manually.
A high-level synthesis method according to the present invention is provided for synthesizing a register transfer level logic circuit based on a behavioral description in which processing behaviors are described. The method includes the steps of extracting information on a bus connection resource from the behavioral description, storing the information on the bus connection resource in a a bus connection resource database, referencing the bus connection resource database, referencing a bus protocol library having a preloaded bus protocol, and automatically generating a target interface circuit based on a result of each of the bus connection resource database referencing step and the bus protocol library referencing step. Thereby, the above-described object of the present invention is achieved. A high-level synthesis apparatus according to the present invention is provided for synthesizing a register transfer level logic circuit based on a behavioral description in which processing behaviors are described. The apparatus includes a bus connection resource extracting section for extracting information on a bus connection resource from the behavioral description, a bus connection resource database for storing the information on the bus connection resource relating to a communication path, a memory, and a register to be connected to a bus, a bus protocol library for storing a bus protocol in advance, and a bus interface generating section for automatically generating a target interface circuit by referencing the bus connection resource database and the bus protocol library.
Accordingly, a bus connection resource database and a bus protocol library are referenced. Therefore, a bus interface circuit, which is conventionally designed by manual work, can be automatically synthesized. An RT level circuit of an entire circuit including the bus interface circuit can be synthesized based on a behavioral description. Therefore, it is easy to manage resources within a circuit, and errors which are inevitable in manual design are eliminated, whereby design quality is improved and a period of time for design is shortened.
Preferably, the high-level synthesis method of the present invention further includes referencing the bus connection resource database to automatically generate a preloaded software header file for a target bus. Further, preferably, the high-level synthesis apparatus of the present invention further includes a preloaded software header file generating section for automatically generating a preloaded software header file relating to a target bus by referencing the extracted information on the bus connection resource and the bus connection resource database.
Accordingly, if a CPU is present in a system, a header file is automatically generated by referencing information on resources. The information on resources which are conventionally managed by manual work can be automatically managed, whereby design quality is improved and a period of time for design is shortened.
Preferably, the high-level synthesis method of the present invention further includes referencing the bus connection resource database to automatically generate a preloaded software library function for a target bus. Further, preferably, the high-level synthesis apparatus of the present invention further includes a preloaded software library function generating section for automatically generating a preloaded software library function relating to a target bus by referencing the extracted information on the bus connection resource and the bus connection resource database.
Accordingly, if a CPU is present in a system, a library function is automatically generated by referencing information on resources. The information on resources which are conventionally managed by manual work can be automatically managed, whereby design quality is improved and a period of time for design is shortened.
Preferably, the information on the bus connection resource includes information on a communication path, a memory and a register to be connected to a bus.
Further, a method is provided for producing a logic circuit using the high-level synthesis method of the present invention.
Furthermore, a computer readable recording medium is provided for storing a computer program for executing the high-level synthesis method of the present invention.
Thus, the invention described herein makes possible the advantages of providing a high-level synthesis method and apparatus for automatically generating a bus interface circuit, which performs data transfer to and from an external circuit, from a behavioral description, and a high-level synthesis apparatus using the method, and a method for producing a logic circuit using the high-level synthesis method, and a recording medium.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.